Power management and, in particular, voltage regulation has been recognized as an important consideration associated with the design and operation of VLSI (Very Large Scale Integration) chips. Consequently, various approaches exist to limit the amount of variation in the supply voltage. Examples of available approaches include the use of a coupling capacitance, dense power grid metal and active voltage regulation.
Existing voltage regulation approaches tend to focus on reducing voltage droop or undershoot. Limiting the amount of voltage droop is important since it impacts the maximum speed at which the VLSI device can operate. Because transistor speed is dependent on supply voltage, for example, a decrease in the supply voltage results in a corresponding reduction in the transistor switching speed, thus reducing the overall operating speed and performance of the VLSI device.
Another consideration in voltage regulation relates to voltage overshoot. Voltage overshoot, for example, occurs when operation of the chip is suddenly terminated, such that there is a sudden decrease in current consumption across the chip. By design, the power delivery system (e.g., the package and power grid), is inductive in nature and thus maintains current flow even though power is not being consumed at the same rate. Thus, an abrupt decrease in current consumption can cause a corresponding voltage spike or overshoot. The overshoot can cause damage to transistors such as through gate oxide wear out and punch through, for example. Accordingly, it is desirable to reduce overshoot and droop.